Zack Weinberg
mastodon 4.7.3Nerd of all disciplines. Online just barely long enough to remember USENET.
Analog interests include pottery, candlemaking, board games, science fiction and fantasy, photography, and cooking.
New follows welcome, but I probably won't follow back because I can't keep up as is. Also, if you are on a large instance please fill out your profile first so I can tell you aren't a spambot.
Does anyone make MX-compatible mechanical keyswitches that have a tactile bump, but right after that (well before the plunger bottoms out) the resistance gets *much stronger* ?
*Ideally* what I want is for the resistance past the operating point to increase in inverse proportion to the remaining distance to the bottom stop, but that might be difficult to achieve mechanically 😜
CPU architecture in which all instructions that access data in memory *require* you to specify the byte order of the value in memory
31 people · Closed
Let's Encrypt was down for three hours and apparently Caddy doesn't implement exponential backoff when it starts getting 503s from its ACME server, nor does it have the sense to remember the failure across vhosts
so I have received 102 copies of the same error message from my log scanner
CPU architecture in which each register is extended with the standard set of arithmetic-result flags (zero, negative, carry, etc), which are set by anything that writes that register; conditional instructions can read these flags from any register; thus splitting the difference between "one flags re
19 people · Closed
CPU architecture in which there are no asynchronous interrupts, only hardware tasks that can be suspended waiting for an external event
18 people · Closed
